In modern integrated circuits, a very high number of individual semiconductor devices, such as field effect transistors in the form of CMOS, NMOS, and PMOS transistors, resistors, capacitors and the like, are formed on a single chip area. However, such semiconductor devices should be properly isolated from one another to function properly. When semiconductor devices are not properly isolated from one another, leakage currents may occur, causing power dissipation, unwanted electric fields, noise-margin degradation, and voltage shift on dynamic nodes.
Shallow trench isolation (STI) structures improve electromagnetic isolation between semiconductor devices. To form an STI structure, typically a narrow trench is formed in a semiconductor substrate and the trench is filled with an insulating material prior to fabrication of semiconductor devices.
After filling the trench, it is sometimes found that sharp corners or divots form in the isolation material during processes such as etching and deglazing. To reduce the tendency of such sharp corners and divots to form, the technique of nitride pull back was developed. During the nitride pull back process, a nitride layer is formed over the substrate and the STI trench is etched through the nitride layer and into the substrate. Nitride pull back involves laterally recessing the edge of the nitride layer from the corner of the STI trench at the interface between the substrate and nitride layer to form a broader corner or shoulder from the substrate. The trench and lateral recesses are then filled with isolation material. This technique allows the deposited isolation material to extend upward and outward from the isolation trench over the trench corners, thereby reducing the tendency of sharp corners or oxide divots to form in the trench isolation material during subsequent processing.
Even after implementing nitride pullback, however, the profile shape of trench corners formed by the substrate may be sufficiently sharp or angular to allow formation of strong electrical fields at these corners that interfere with the operation or performance of adjacent medium or high voltage semiconductor devices. These unintentional electric fields interfere by, for example, producing undesirable kinks in the I-V characteristics of the adjacent and/or other nearby semiconductor devices, as well as generating higher off-current and degrading any gate oxide. These issues are of less concern for low voltage devices (i.e., semiconductor devices having operating voltages of no more than about 1.4 V), but become more severe in the presence of medium and high voltage devices (i.e., semiconductor devices having operating voltages of at least about 5 volts (V). Other techniques for forming more rounded trench corners that would minimize or avoid these problems for medium and high voltage devices presently exist. However, using those same techniques for forming trench corners proximate low voltage devices on semiconductor devices and integrated circuits often causes other problems including excessive silicon consumption and inability to meet strict active design requirements.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that have a low voltage device, as well as a medium voltage device, a high voltage device, or both, and STI trenches between the different voltage devices that have different trench corners suitable to properly isolate the different voltage devices. In addition, it is desirable to provide methods for fabricating device substrates having different voltage regions with STI trenches defining different voltage device-forming areas therein and having different trench corners suitable for different voltage devices to be formed thereon. Furthermore, other desirable features and characteristics of the methods and apparatus contemplated herein will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings.